The present invention relates to PIN-FET devices. Future interfaces between optical and electronic components of optical data transmission systems will contain monolithically integrated optoelectronic circuits. The problem of the integration of a photodetector and a preamplifier arises at the receiver side. What are required are good compatibility of the semiconductor layers and technologies needed for the various components. One difficulty in the monolithic integration of a photodiode with a field effect transistor (FET) lies in the different demands made of the doping concentrations and layer thicknesses.
For a high external quantum efficiency, an optimized photodiode requires an adequately thick absorption layer of, for example, n-InGaAs in the InGaAsP material system with low residual doping. This nominally undoped InGaAs layer is a prerequisite for a low capacitance as well as a low dark current, and, consequently, for good noise properties. The p.sup.+ -region into which the light is incident through an annular p-contact is fashioned in an n-doped cover layer of InP or InAlAs. A highly doped, n-conductive semiconductor layer of, for example, InGaAs, InP or InAlAs for reducing the series resistance and the transit time effects, i.e. the carrier transit time in the diode is applied between the absorption layer and the substrate of, for example, semi-insulating InP:Fe. The n-contact is applied on this highly doped semiconductor layer.
For a high transconductance, the FET requires a highly doped n-InGaAs layer as channel layer that must be correspondingly thin for a good cut-off behavior of the FET. A lightly doped n-InGaAs layer as buffer layer that prevents disturbing influences from the substrate (out-diffusion of iron into the channel layer) follows in the direction toward the substrate of, for example, InP:Fe. The p.sup.+ -doped region that is laterally limited and provided with a contact is situated on the channel layer. The contacts for drain and source are applied on the channel layer. The condition for the insertion of the buffer layer is that the cut-off behavior of the FET is not negatively influenced, i.e. this buffer layer cannot be excessively thick (less than 2 .mu.m) and the doping cannot be excessively high (less than 10.sup.15 cm.sup.-3). The cover layer that forms the gate is n-InP or, respectively, n-InAlAs and forms a heterobarrier toward the InGaAs of the channel layer and enables the realization of a blocking metal-to-semiconductor junction as gate. This layer also has the advantage that a passivation of the pn-junction and the component surface increases the long-term stability and reduces leakage currents due to the higher band spacing of InP or, respectively, InAlAs in comparison to InGaAs. This advantage is valid both for a PIN or photodiode (PD) as well as for the FET.
In order to avoid complicated epitaxy processes (for example, surface-selective epitaxy) or, respectively, the erosion of individual epitaxy layers in the integration of PD and FET, compromises are made with respect to the layer structure.
German published application DE 37 11 617 Al discloses a PD-FET combination wherein a lightly n-doped InGaAs layer and a highly n-doped InGaAs layer thereon are grown-surface wide and wherein a n.sup.+ -implantation had been selectively produced before the epitaxy in the region of the photodiode in the substrate.